Constant ON-time controllers are used in a class of buck regulators that use the output voltage ripple to initiate an ON-time whenever the regulator output voltage falls below a reference voltage. The ON-time is terminated (generating an ON-time pulse) by circuitry in response to other conditions (e.g., level of regulator input). During the ON-time pulse, energy is supplied directly from the regulator input voltage to the regulator output via an electronic switching device. Likewise, when the ON-time pulse has terminated, stored energy from the regulator input voltage is supplied to the regulator output. Most constant ON-time regulators include circuits that adjust the ON-time pulse duration as a function of the regulator input voltage and regulator output voltages, thus resulting in an almost constant frequency as the duty cycle changes. The regulator output voltage ripple is determined to a large extent by the ripple current in the energy storage inductor flowing through the output capacitor's equivalent series resistance (ESR). In applications that require low voltage ripple; the ESR must be very small. This creates two problems for constant ON-time controllers, stability and susceptibility to noise. Some circuits use techniques that supplement the ESR generated ripple with a voltage ramp. These voltage ramps minimize the susceptibility of the controller to noise and thus substantially reduce jitter.
A typical constant ON-time controller for a buck regulator is shown in FIG. 5. The output voltage (Vout) 516 is set by a duty cycle that is defined as the ratio of ON-time of the high-side field effect transistor (FET) 507 to the total switching period. Whenever Vout 516 drops below the reference voltage Vref 517, comparator 508 sets latch 509. Gate drivers 508 turn FET 507 ON thereby charging inductor (L) 504 and delivering current to the load (not shown) coupled to Vout 516. Latch 509 remains set until the voltage 518 across capacitor (C) 511 exceeds Vref 517. At this time, comparator 510 resets latch 509 and gate drivers 500 turn FET 507 OFF and FET 506 ON. The energy stored in L 504 causes the load current to continue to flow to Vout 516. Catch diode (D) 505 insures current in L 504 is not interrupted during switching to minimize transients.
The ON-time (time interval FET 507 is ON) is a function of both Vin 515 and Vref 517. As Vin 515 rises, the ON-time will be shorter since C 511 charges faster. If Vref 517 is increased, C 511 has to charge to a higher voltage to trip the comparator 510, also resulting in a longer ON-time. Thus, the circuitry adjusts the ON-time to minimize the frequency changes (as determined by the time between pulses) that would otherwise result from changes in Vin 515 and Vout 516. To increase the current in inductor (L) 504 in response to a step change in the load (not shown) coupled to Vout 516, the control loop generates more ON pulses per unit time. To decrease the current in L 504, the control loop generates fewer pulses per unit time. Therefore, during transient load steps the frequency is not constant.
Multi-phase buck converters are used in applications that demand high output currents. They may be constructed by connecting two or more buck converters to the same output capacitor. The control loop for a multiphase buck converter must regulate the output voltage and ensure that the inductor in each phase has the same current. Multi-phase buck controllers are popular in low voltage, high current applications that require a fast transient response. They are often used to generate the supply voltage for the central processing unit (CPU) integrated circuit (IC) in desktop and notebook computers. Voltage mode, current mode, and hysteresis type controllers have all been used successfully to control the output voltage in these applications. However, converters with these types of controllers require a second current loop to match the current from each converter since it is desirable to have each converter provide an equal share of the load current. Therefore, in a dual phase buck converter, the energy storage inductor in each converter should normally supply half the load current. Likewise, in a three-phase converter system, the inductor in each phase should normally supply one third of the load current.
Current mode controllers are a popular choice for multiphase controllers because their current loop can regulate the current sharing in each phase. But hysteresis and constant ON-time controllers may also be used when a second current loop is added to force current sharing. Current sharing may be controlled either on an average basis or on a cycle-by-cycle basis. If average current sharing is used, then the bandwidth of the current control loop must be very low. As the current is adjusted by changing the duty cycle, it will take time for the inductor current to change. This delay makes average current sharing difficult to implement. The most likely way to ensure that average current sharing stable is to design the response of the current control loop to be very slow. This may not be desirable since during the occurrence of a current imbalance it will take many cycles for the control loop to correct the imbalance. On the other hand, peak current sharing can control the current sharing on a cycle-by-cycle basis. A system employing peak current sharing is easy to stabilize and can correct for unequal current sharing quickly.
FIG. 1A is a simplified block diagram of a dual phase buck regulator with constant ON-time control and active current sharing. The output capacitor (C) 102 is usually a network of many capacitors in parallel. The equivalent series resistance (ESR) represented by resistor ESR 101 is the effective series resistance of this capacitor network. ESR 101 is the real part of the complex impedance of the network of parallel capacitors making up C 102. Two sense resistors, R 137 and R 103, provide voltages VR2 127 and VR 1122 that are proportional to the current in inductors 117 and 104 in each phase, respectively. VR1 122 is the difference in potential between node 124 and Vout 130 and VR2 127 is the difference between node 131 and Vout 130. The four field effect transistors (FETs), FET 106, FET 107, FET 116, and FET 118 control the duty cycle of each phase. Diodes 105 and 115 are flyback diodes that insure the currents in the inductors 104 and 117, respectively, are not interrupted. The gate drivers 119 and 120 in phase drive circuits 180 and 181 interface with the control circuit 121 and provide the voltages needed to drive FETs 106, 107, 116 and 118. The control circuit 121 determines which of the two phases, 180 or 181, to turn ON when the output voltage (Vout) 130 falls below the reference voltage (Vref) 123. The output currents IL1 141 and 1L2 I42 combine to provide load current lout 160 to load 140.
FIG. 1B illustrates the timing of two converter phases 180 and 181. The two graphs in FIG. 1B show that by complementary switching the two converter phases 180 and 181, both the amplitudes of the output current ripple (Iout 160) relative to output currents IL1 141 and IL2 142 and output voltage ripple (Vout 130) relative to sense voltages VR1 127 and VR2 122 are cut in half and the ripple frequency is doubled.
FIG. 2 is a circuit diagram of an open loop constant ON-time buck controller for dual converters. The output 240 of the comparator 229 is coupled to an input of AND gates 230 and 231. The outputs 241 and 242 of flip flop (FF) 228 are coupled to the other inputs of AND gates 230 and 231 respectively. Outputs 241 and 242 alternately turn ON each converter phase (280 and 281) when Vout 250 drops below the reference voltage (Vref) 217. The pulse circuits 225 and 226 and OR gate 227 provide the clock to the FF 228. FF 228 is configured as a “D-type” FF that changes state on each positive clock edge (of its CLK input). Therefore, since each pulse from pulse circuits 225 and 226 are logic ORed in OR gate 227 to form clock 252, each pulse causes outputs 241 and 242 of FF 228 to switch states. When output 242 is logic one, AND gate 231 is enabled and latch 220 in the converter phase 281 is set when the output of comparator 229 (coupled to 240) transitions to logic one. When latch 220 is set, FET 218 turns ON (via gate drivers 219) charging inductor L 227 and providing current to Vout 250. Conversely, if output 241 is logic one, then AND gates 230 is enabled and latch 209 in converter phase 280 is set when the output of comparator 229 transitions to logic one turning ON FET 207 (via nate drivers 208) charging inductor L 204 and providing current to Vout 250. Latches 209 and 220 are reset by comparators 210 and 221 when the voltages on capacitors 211 and 222, respectively, exceed Vref 217. Capacitors 211 and 222 are discharged by FETs 212 and 224. Sense resistors 203 and 245 are used to sense the current in inductors 204 and 227, respectively. FETs 206 and 216 and diodes 205 and 225 insure the currents in the charging inductors are not interrupted. Capacitor 201 is the load filter capacitor and resistor 202 represents its ESR.
In both cases, the ON-time pulse commences by setting a latch 209 for converter phase 280 and latch 220 for converter phase 281. The latch 209 signals gate drivers 208 to turn high-side FET 207 ON and latch 220 signals gate drivers 219 to turn FET 218 ON. The timing circuits (outputs of comparators 210 and 221 respectively) reset each corresponding latch (latch 209 and latch 220, respectively) after a fixed ON-time. Resetting latch 209 turns high-side FET 207 OFF and resetting latch 220 turns FET 218 OFF. Depending on which phase is active, low-side FET 205 and FET 216 are turned ON when corresponding latches 209 and 220 are reset.
The constant ON-time timing circuits are set up so that the ON-time pulses HSON1 285 and HSON2 286 are proportional to the Vref 217 and inversely proportional to Vin 215. Thus, if Vin 215 increases, the current in through R 213 and R 223 will also increase. An increase in Vin 215 will cause capacitors C 211 and C 222 to charge faster resulting in a shorter ON-time. If the Vref 217 increases, C 211 and C 222 will have to charge to a higher voltage to switch comparators 210 and 221, respectively, resulting in longer ON-times. This constant ON-time circuit maintains a nearly constant frequency as Vin 215 and Vref 217 vary. However, circuit 200 does not have adequate performance because even small errors in the ON-time pulse width may result in very large current sharing errors. Because of the possible large current sharing errors, a current control loop (not shown) must be added to actively adjust the pulse width to minimize current sharing errors.
FIG. 3 is a circuit diagram of circuit 300 that has the function of a closed loop average current sharing constant ON-time buck converter. The output 340 of the comparator 329 is coupled to one input AND gates 330 and 331. The outputs of flip flop (FF) 328 are coupled to positive edge delay circuits 388 and 389. Positive edge delay circuits 388 and 389 delay the rising edges of outputs 341 and 342 which in turn alternately turn ON each converter phase when Vout 350 drops below the reference voltage (Vref) 317. Pulse circuit 325 receives ON-time pulse (HSON1 385) from latch 309. Pulse circuit 326 receives ON-time pulse (HSON2 386) from latch 320. HSON1 385 and HSON2 386 are logic ORed in OR gate 327 to provide the clock to the FF 328. FF 328 is configured as a “D-type” FF that changes state on each positive clock edge. Therefore, since each pulse from pulse circuits are logic ORed in OR gate 327 to form clock 352, each pulse causes the outputs of FF 328 to switch states. When output 341 is logic one, AND gate 330 is enabled and latch 320 in the converter phase 381 is set when the comparator 329 transitions to logic one. When latch 320 is set, FET 318 turns ON charging inductor L 327 and providing current to Vout 350. Conversely, if output 342 is logic one, then AND gate 331 is enabled and latch 309, in converter phase 380, is set when the output of comparator 329 transitions to logic one.
Diodes 306 and 325 insure the currents in inductors 304 and 327 are not interrupted during switching. Load filter capacitor 301 has ESR 302. Gate drivers 308 and 319 provide drive voltages to FETS 305, 307, 316 and 318. FETs 213 and 324 discharge capacitors 311 and 322 in response to reset signals from latches 309 and 320 generated when the voltages of capacitors 311 and 322 exceed Vref 317 and the outputs of comparators 310 and 321 transition to a logic one.
In both cases, the ON-time pulses commence by setting a latch 309 for converter phase 380 and latch 320 for converter phase 381. Latch 309 signals gate drivers 308 to turn high-side FET 307 ON and latch 320 signals gate drivers 319 to turn FET 318 ON in converter phase 381. The timing circuits (output of comparators 310 and 321) then reset each corresponding latch (latch 309 and latch 320, respectively) after a fixed ON-time. Resetting latch 309 turns high-side FET 307 OFF and resetting latch 320 turns FET 318 OFF . Depending on which phase is active, low-side FET 305 and low-side FET 316 are turned ON when corresponding latches 309 and 320 are reset.
If HSON1 385 transitions to logic one, then both inputs 341 and 342 of AND gate 330 are at logic one. The positive transition of HSON1 385 triggers pulse circuit 325, which clocks FF 328 so that its Q output transitions to logic zero thereby degating AND gate 330 thus removing the set input to latch 309. Since the Q output of FF 328 transitions to logic zero, its complementary output (input to positive edge delay circuit 389) transitions to logic one. Without the positive edge delay of Edge Dly 389, converter phase 381 would turn ON as soon as converter phase 380 turned ON and Vref 317 is greater than Vout 350. Edge Dly 388 and Edge Dly 389 guarantee that there will be a period of time when both phases cannot be ON concurrently whenever Vref 317 is greater than Vout 350
The constant ON-time circuit in converter phase 380 is configured such that the ON-time pulse (HSON1 385) is proportional to the Vref 317 and inversely proportional to Vin 315. Thus, if Vin 315 increases the current in through R 313 will also increase. An increase in Vin 315 will cause capacitor C 311 to charge the faster resulting in a shorter ON-time. If the Vref 317 increases, C 311 will have to charge to a higher voltage to switch comparators 310, resulting in a longer ON-time. This constant ON-time circuit maintains a nearly constant frequency as Vin 315 and Vref 317 vary. Converter phase 381 is designed to be a slave to converter phase 380 in that the voltage for charging C 322 to set its ON-time (HSON2 386) is no longer a function of Vin 315 but rather feedback voltage 354.
Transconductance amplifiers (GMA) 332 and GMA 334 each sense the voltage across their corresponding sense resistors R 303 and R 337. GMA 332 and GMA 334 generate currents IR 370 and IR 371, respectively. IR 370 flows through resistor R 336 generating voltage 373 and IR 371 flows through R 335 generating voltage (V) 372. V 372 and V 373 are proportional to the voltage drops across their corresponding sense resistors R 337 and R 303. GMA 333 converts the difference between V 372 and V 373 to a current IR 375, which produces a voltage at node 354 as current IR 375 is integrated by C 322. When FET 324 is turned OFF (HSON2 386 is logic one), C 322 charges to Vref 317 to switch comparator 321 and reset latch 320 terminating the ON-time pulse to converter phase 381.
R 336 is coupled to the negative input of GMA 333 and R 335 is coupled to the positive input of GMA 333. If the current through sense resistor R 303 (converter phase 380) is larger than the current through sense resistor R 337 (converter phase 381), then the feedback is such that current IR 375 decreases thus lengthening the ON-time for converter phase 381 and increasing the current from converter phase 381. The output current of GMA 333 determines the ON-time pulse width of converter phase 381. Thus, GMA 333 will trim the ON-time pulse width of converter phase 381 until its output current substantially matches the output current in converter phase 380. Since the current of GMA 333 is always positive, the current in sense resistor R 303 is always slightly larger (determined by the gain of GMA 333) than the current in sense resistor R 337. The drawback to this technique is that it is hard to stabilize. After an ON pulse is trimmed, the new steady state current will be delayed for several switching cycles. The bandwidth of GMA 333 must be very low or the system may oscillate. Furthermore, since GMA 333 must have a very low bandwidth, it will take many switching cycles for this system to correct for current sharing errors.
Therefore, a need for control circuitry for a multiphase constant ON-time buck controller that insures current matching between the converter phases with small current sharing errors and fast response time to load changes.